Gidel FPGA Boards | High performance scalable compute acceleration systems | I/O flexibility | FPGA development tool kits| FPGA IP cores

The Gidel Proc10S high performance scalable compute acceleration board is powered by an Intel Stratix 10 FPGA with up to 200 Kle, 260 GB DDR4 RAM, and an option for a SoC Quad-core 64-bit ARM Cortex-A53 MPCore processor. Peak single precision performance reaches 10 TFLOPS.

Gidel’s Proc10M / Proc10N module is designed to enable easy use and immediate accessibility to the powerful Intel Stratix 10 FPGA with HBM2 on-chip memory technology for both host and embedded systems.

The Proc10A™ system is a flexible, high performance, low-power FPGA platform based on Intel’s powerful Arria 10 FPGA. The Proc10A offers high I/O throughput and high powered on-board processing and data management for low latency for applications such as HPC high performance computing, storage, networking, and high-end imaging.

The HawkEye is a PCIe 8 lane Gen 3 low profile board based on Intel’s Arria 10 FPGA. This compute accelerator has up to 18 GB DDR4 on-board memory, up to four SFP+ links for a maximum of 56 Gbs. The Arria 10 FPGA provides up to 480K LEs and IEEE floating-point numbers.

Gidel offers a number of ultra-compact high-performance FPGA modules that can be mounted on a PCIe carrier board. The modules provide a complete FPGA envelope ready for use while leaving flexibility to tailoring the peripheral system precisely. Gidel provides templates and powerful development tools that enable quick development and optimal FPGA utilization. 

The Gidel JPEG Compression FPGA IP Core encodes JPEG at high-performance. The compression IP is fast processing, low latency, and compact silicon utilization. The IP can compress high-performance camera image streams on a small FPGA device, or alternatively, multiple instances can run on a single larger FPGA device.

Gidel’s lossless compression FPGA IP Core is real-time compression for Color Filter Arrays such as Bayer, Monochrome, and RGB images and videos. The IP enables compression of multiple cameras or sensors at pixel clock rates exceeding 1 Giga pixels.