Gidel has 25 years experience developing high-end FPGA systems as products for sale or as integration projects for customers using a combination of industry standard tools such as OpenCl, and internal advanced development tools, which are also available to end-customers.
Gidel products, tools, and expertise are used in applications including security, DNA research, machine learning, imaging and vision systems, augmented and virtual reality, deep learning, and reconfigurable interconnect frameworks for HPC clusters.
An intelligent FPGA solution for high performance FPGA acceleration from Gidel requires speed, compute efficiency, and best use of memory capacity and bandwidth.
Gidel has the knowledge, experience, and has developed extremely stable tools based on the latest technology to reduce development time and effort and to ensure long product life cycles.
Sky Blue Microsystems GmbH of Munich, Germany, provides advanced electronics products for science and industry, and is an international distributor for Gidel.
Gidel’s Total History IP Core is an innovative signal tracing tool for FPGA prototyping enabling virtually unlimited signal trace depth, and massive and flexible probing of real system performance. TotalHistory uses the unused on-board memory and memory bandwidth of the FPGA boards, thus requires no additional resources.
GiDEL’s novel TotalHistory IP opens the way to unprecedented design visibility. TotalHistory is based on a unique design-embedded IP core. Probes are inserted at any design point of interest to capture signals at full operating speed; signal trace is stored in the on-board memory or on peripheral SODIMMs at practically unlimited depth (up to 8.5 GB/FPGA) enabling virtually infinite signal tracing regression to accurately detect, reproduce, and isolate system bugs. Real-time signals are channeled to the host allowing user application processing to generate complex triggering schemes to detect bugs and to capture vital internal signal states. Once a trigger is issued, virtually infinite signal trace history can be retroactively analyzed by the host application, or by a simulator via the PCI/e bridge, or via Gigabit Ethernet (in the case of a PROC_SoCTM system). TotalHistory can support as much as 100,000 fully configurable probes per FPGA permitting comprehensive signal visibility.
Gidel’s InfiniVision technology allows development of Augmented and Virtual Reality products to utilise high quality image content from a large camera arrays to generate 360 degree panoramas for the latest immersive entertainment and sports experiences.
Gidel’s low-latency, full duplex direct FPGA connectivity technology allows customers to build Reconfigurable Interconnect Frameworks for HPC clusters with no CPU overhead. 3D and 12D Torus and 6D and 24D Hypercube topologies can be optimized to become the HPC infrastructure required for compute-intensive workloads.
The Gidel Developer’s Suite is based on 25 years of continuous improvement. Developer’s Suite gives you unmatched development productivity. The Gidel Developer’s Suite consists of:
Proc Developer’s Kit (ProcDev Kit), as an alternative to existing FPGA design methodologies. It is oriented towards implementing your algorithms in a user friendly and efficient manner.
HLS Application Support Package (I++) allows you to use Intel’s High Level Synthesis (HLS) tool, which generates Register Transfer Level (RTL) from C++ input. The output is optimized for FPGAs.
Gidel supports Intel’s Open Vino Artificial Intelligence and Machine Learning libraries.
Gidel supports Halcom’s MVTec comprehensive standard software for machine vision applications.
Gidel provides OpenCL Board Support Packages (BSPs) for FPGA compute accelerating.
The Gidel HawkEye-CL frame grabbing and real-time image processing system provides the core infrastructure required to support the most demanding Vision and Imaging applications. The HawkEye-CL is Camera Link Rev. 2.0 compliant and supports 80-bit Camera Link modes, including 10-bits/8-tap and 8-bit/10-tap modes.
More…The Gidel Proc10A eight channel CoaXPress frame grabbing and real-time image processing system provides the core infrastructure required to realize the most demanding vision and imaging applications.
More…The Gidel HawkEye 10GigE Vision frame grabbing and real-time image processing system supports link aggregation, chunk data transmission, ROI capture capability, and comprehensive system I/Os.
More…The Gidel HawkEye-CXP-12 four channel CoaXPress frame grabbing and real-time image processing system provides the core infrastructure required to realize the most demanding vision and imaging applications.
More…Gidel’s FantoVision family is a pioneering compact computer enabling image acquisition and processing using CoaXPress, CameraLink, or 10GigE Vision over 1-4 10G links. The FantoVision’s innovative architecture merges high-end image acquisition with real-time image processing and or compression using an Nvidia Jetson™ embedded GPU with optional pre-processing/compression on an Intel FPGA.
More…The Gidel CamSim™ is a flexible high-performance camera simulator that generates a camera link video stream and test patterns for testing frame grabbers or vision/imaging systems. The system supports all Camera Link™ specification v2.0 configurations and can be customized for any user-defined camera protocol and interface.
More…The Remote Camera Link Fiber-Optic (RCL) extension system allows frame acquisition from a remote camera at a distance of up to 40 km without repeaters. A remote camera connects directly to the RCL module, which transmits the camera image over fiber optic cable.
More…The Gidel JPEG Compression FPGA IP Core encodes JPEG at high-performance. The compression IP is fast processing, low latency, and compact silicon utilization. The IP can compress high-performance camera image streams on a small FPGA device, or alternatively, multiple instances can run on a single larger FPGA device.
More…Gidel’s lossless compression FPGA IP Core is real-time compression for Color Filter Arrays such as Bayer, Monochrome, and RGB images and videos. The IP enables compression of multiple cameras or sensors at pixel clock rates exceeding 1 Giga pixels.
More…The Gidel Proc10S high performance scalable compute acceleration board is powered by an Intel Stratix 10 FPGA with up to 200 Kle, 260 GB DDR4 RAM, and an option for a SoC Quad-core 64-bit ARM Cortex-A53 MPCore processor. Peak single precision performance reaches 10 TFLOPS.
More…Gidel’s Proc10M / Proc10N module is designed to enable easy use and immediate accessibility to the powerful Intel Stratix 10 FPGA with HBM2 on-chip memory technology for both host and embedded systems.
More…The Proc10A™ system is a flexible, high performance, low-power FPGA platform based on Intel’s powerful Arria 10 FPGA. The Proc10A offers high I/O throughput and high powered on-board processing and data management for low latency for applications such as HPC high performance computing, storage, networking, and high-end imaging.
More…The HawkEye is a PCIe 8 lane Gen 3 low profile board based on Intel’s Arria 10 FPGA. This compute accelerator has up to 18 GB DDR4 on-board memory, up to four SFP+ links for a maximum of 56 Gbs. The Arria 10 FPGA provides up to 480K LEs and IEEE floating-point numbers.
More…Gidel offers a number of ultra-compact high-performance FPGA modules that can be mounted on a PCIe carrier board. The modules provide a complete FPGA envelope ready for use while leaving flexibility to tailoring the peripheral system precisely. Gidel provides templates and powerful development tools that enable quick development and optimal FPGA utilization.
More…The Gidel Proc Developer’s Kit (ProcDev Kit) is an easy to use FPGA design tool. It optimises on-board memory and host communication in support of your algorithm implementation on the FPGA. The Developer’s kit includes the ProcWizard application, an API, Gidel IPs, examples, and HDL and software libraries.
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