Plasma etching produces a patterned, thin film deposit on a substrate. This film is covered by a thin layer (< 1 μm) of photoresist mask, which is patterned by exposure to ultraviolet light. The patterned wafer is then exposed to low-temperature plasma doped with etch chemicals that selectively remove the underlying thin film in the pattern allowed by the photoresist layer. The wafer is then stripped to remove the mask and cleaned. This process is then repeated for the next layer. The steps of the wafer fabrication process are illustrated in Figure 1.
Figure 1. Steps of typical wafer fabrication process.
In the etch stage, the patterned wafer is placed in a plasma reactor. When the plasma is turned on, the impacting electrons dissociate the molecules into reactive species. Without additional control, the etching will proceed uniformly in all directions, which will undercut the patterned mask. This isotropic etch process is not suitable for many processes including the fabrication of high aspect ratio (HAR) features. HAR features with aspect ratios near 100:1 are becoming increasingly important in the production of NAND flash, which is driven by the rapidly increasing demand for solid-state, non-volatile memory storage. The market demand is pushing for higher bit densities and lower bit costs. In 2015, NAND critical dimensions (CDs) were reduced to ~30 nm. Shrinking beyond ~15 nm with current capabilities is likely cost prohibitive. Additionally, coupling between neighboring cells is also becoming problematic. The technological roadmap for memory production is moving from 2D NAND processes, which are limited by lithographic and device constraints, to vertical 3D architectures. These 3D architectures require techniques that can control feature size variations while etching HAR features in high-volume manufacturing.
Two major challenges with the production of HAR features for 3D NAND are controlling distortions in the etched profile and CD uniformity at the HAR bottom. Figure 2 shows the challenges that arise in more complex 2D and 3D HAR features. HAR etching requires longer processing time, and higher etch rates are needed to reduce overall cost. In order to etch modern high quality HAR features with small CD, precision control of the ion energy distribution (IED) is required, and higher power levels are required to increase the etch rate and reduce costs. If anisotropic IED can be produced such that most of the energy is in the direction perpendicular to the material surface, the vertical etch rate can be significantly increased without significant sidewall etching. In modern etching systems, these system features need to be carefully controlled to have a viable process:
Etch rate and wafer throughput
Selectivity (relative etch rates of different
materials)
Anisotropy (vertical vs horizontal etch
rate)
Feature profile dimensions, shape, and
quality
Uniformity across the wafer
Repeatability of the process from wafer to wafer and chamber to chamber
Figure 2. Fabrication of vertical gate stack structures requiring HAR etching, resulting dimensional scaling from 2D to 3D.
The Semiconductor Fabrication Plasma Etching Chamber
Figure 3 shows an illustration of a typical plasma etching system. Plasma is typically created by a capacitively coupled plasma (CCP) source, which is an electrode in the chamber that is driven by a radio frequency (RF) generator. Alternatively, plasma can be produced by an inductively coupled plasma (ICP) source (not shown). The wafer is placed on a second electrode that is sitting on the chuck. A second power system, which may consist of one or more RF generators, is used to bias the wafer. The voltage supplied by the bias power system draws ions to the wafer surface. This bias power system is responsible for the IED at the wafer surface. RF generators do not provide users with many control parameters that can be used to control the plasma process at the wafer surface. The frequency is one control parameter; however, most RF generators cannot change their frequency by significant amounts. The other control parameter is power. Increasing the power of an RF generator will increase the wafer bias voltage and increase the energy of the ions reaching the wafer surface. RF generators require a matching network for proper power transfer, both on the plasma production side and the wafer bias side. The use of a matching network limits the direct control of the waveform on the wafer, does not allow for feedback and control on plasma timescales, and is complex to use and operate. The RF era of bias is ending.
Figure 3. Capacitively coupled plasma (CCP) source with topside RF generator for plasma production and multiple RF generators for wafer bias.
EHT Semi Semiconductor Fabrication Products
The EHT Semi plasma products achieve the highest semiconductor fabrication etch quality with precision control of the ion energy distribution (IED) at lowest minimum critical dimensions, yet with etching rates comparable to RF generators.
Our product range for semiconductor fabrication is summarized in the following table. Click any link for further information:
